1. Field of the Invention
The present invention relates to a semiconductor device having a ball grid array (BGA) package structure that is provided with a substrate for mounting a semiconductor chip thereon. This is counterpart of and claims priority to Japanese Patent Application No. 372783/2003 filed on Oct. 31, 2003, which is herein incorporated by reference.
2. Description of the Related Art
With increasing dissemination of small electronic equipment typically represented by mobile telephones, there has been increasing demand for smaller semiconductor devices installed in such equipment. To reduce the sizes of semiconductor devices, efforts have been made to increase the packaging density of the semiconductor devices. As one example of the efforts, semiconductor devices having the BGA package structure have been put into practical use.
A semiconductor device having the BGA package structure is equipped with a substrate for mounting a semiconductor chip thereon, the substrate having a built-in wiring structure. The wiring structure is constructed of interconnections, which serves as electrically conductive paths, extended in the substrate and on both main surfaces thereof.
A solder resist layer serving as an insulating protective film is formed on the interconnections. A semiconductor chip is mounted on the substrate by bonding it onto the solder resist layer through the intermediary of a die bonding layer composed of an adhesive insulating paste or the like. Both electrodes of the semiconductor chip and the interconnections are electrically connected by electrically conductive metal interconnections, such as gold interconnections. This means that the electrodes of the semiconductor chip and an external electrode terminal are electrically connected through the intermediary of the metal interconnections and the wiring structure built in the substrate. The semiconductor chip and the metal interconnection are hermetically secured onto one main surface of the substrate by a sealing resin.
It is known, however, that in the structure wherein the interconnections are disposed below an outer edge of the semiconductor chip through the intermediary of the solder resist layer, when so-called heat cycle durability test or heat cycle test in which semiconductor devices are periodically subjected to temperature changes is carried out, the interconnections below the outer edge of the semiconductor chip tend to break due to stress generated by temperature changes. Efforts have been made to prevent a failure of the semiconductor device attributable to such breaking of interconnections, one example of which has been disclosed in Japanese Unexamined Patent Application Publication No. 11-163201 (Patent Document 1).
According to Patent Document 1, the width of a interconnection disposed in a region located at a position opposing the outer edge of a semiconductor chip is, for example, set to be greater than the width of a wiring pattern disposed in a region that is out of the foregoing region and located at a position opposing areas outside and/or inside the outer edge of the semiconductor chip. Alternatively, interconnections are routed to cross aslant the outer edge of the semiconductor chip. Further alternatively, a semiconductor device is designed to avoid disposing interconnections in a region located at a position opposing the outer edge of a semiconductor chip as much as possible. By adopting these constructions, failures of semiconductor devices caused by broken interconnections are prevented.